Nexperia 74HC273D,653 8-Bit Latch, Addressable, D Type Flip-Flop, 20-Pin SO
- RS Stock No.:
- 170-7978
- Mfr. Part No.:
- 74HC273D,653
- Manufacturer:
- Nexperia
Subtotal (1 reel of 2000 units)*
MYR2,778.00
FREE delivery for orders over RM 500.00
Temporarily out of stock
- Shipping from 10 September 2026
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per Unit | Per Reel* |
|---|---|---|
| 2000 + | MYR1.389 | MYR2,778.00 |
*price indicative
- RS Stock No.:
- 170-7978
- Mfr. Part No.:
- 74HC273D,653
- Manufacturer:
- Nexperia
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Nexperia | |
| Product Type | Latch | |
| Logic Family | 74HC | |
| Logic Function | D Type | |
| Latch Mode | Addressable | |
| Number of Bits | 8 | |
| Output Type | D Type Flip-Flop | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 2V | |
| Package Type | SO | |
| Maximum Supply Voltage | 6V | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Width | 7.6 mm | |
| Series | 74HC | |
| Standards/Approvals | No | |
| Length | 13mm | |
| Height | 2.45mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Nexperia | ||
Product Type Latch | ||
Logic Family 74HC | ||
Logic Function D Type | ||
Latch Mode Addressable | ||
Number of Bits 8 | ||
Output Type D Type Flip-Flop | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 2V | ||
Package Type SO | ||
Maximum Supply Voltage 6V | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Width 7.6 mm | ||
Series 74HC | ||
Standards/Approvals No | ||
Length 13mm | ||
Height 2.45mm | ||
Automotive Standard No | ||
The 74HC273, 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Key applications
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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