Alliance Memory AS4C64M16D3LC-12BCN SDRAM 1 GB Surface, 96-Pin 16 bit FBGA-96 Ball
- RS Stock No.:
- 425-269
- Mfr. Part No.:
- AS4C64M16D3LC-12BCN
- Manufacturer:
- Alliance Memory
Subtotal (1 tray of 198 units)*
MYR17,610.32
Stock information currently inaccessible - Please check back later
Units | Per Unit | Per Tray* |
|---|---|---|
| 198 + | MYR88.941 | MYR17,610.32 |
*price indicative
- RS Stock No.:
- 425-269
- Mfr. Part No.:
- AS4C64M16D3LC-12BCN
- Manufacturer:
- Alliance Memory
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Memory Size | 1GB | |
| Product Type | SDRAM | |
| Organisation | 64M x 16 | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 800MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-96 Ball | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 96 | |
| Maximum Operating Temperature | 95°C | |
| Series | AS4C64M16D3LC | |
| Width | 7.5mm | |
| Standards/Approvals | RoHS, JEDEC | |
| Height | 1mm | |
| Length | 13mm | |
| Minimum Supply Voltage | 1.28V | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.35V | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Memory Size 1GB | ||
Product Type SDRAM | ||
Organisation 64M x 16 | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 800MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-96 Ball | ||
Minimum Operating Temperature 0°C | ||
Pin Count 96 | ||
Maximum Operating Temperature 95°C | ||
Series AS4C64M16D3LC | ||
Width 7.5mm | ||
Standards/Approvals RoHS, JEDEC | ||
Height 1mm | ||
Length 13mm | ||
Minimum Supply Voltage 1.28V | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.35V | ||
- COO (Country of Origin):
- TW
The Alliance Memory 1gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
RoHS compliant
Auto Refresh and Self Refresh
Related links
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