Infineon CYT2B75CADQ0AZEGS, 32 bit ARM Cortex M4, TRAVEO™ T2G CYT2B7 Series Microcontroller, 160 MHz, 1.088MB FLASH,
- RS Stock No.:
- 273-5292
- Mfr. Part No.:
- CYT2B75CADQ0AZEGS
- Manufacturer:
- Infineon
This image is representative of the product range
Subtotal (1 unit)*
MYR109.82
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- Shipping from 20 April 2027
Units | Per Unit |
|---|---|
| 1 - 9 | MYR109.82 |
| 10 - 24 | MYR101.27 |
| 25 - 49 | MYR96.76 |
| 50 - 99 | MYR94.83 |
| 100 + | MYR86.60 |
*price indicative
- RS Stock No.:
- 273-5292
- Mfr. Part No.:
- CYT2B75CADQ0AZEGS
- Manufacturer:
- Infineon
Select all | Attribute | Value |
|---|---|---|
| Brand | Infineon | |
| Product Type | Microcontroller | |
| Series | TRAVEO™ T2G CYT2B7 Series | |
| Package Type | LQFP | |
| Mount Type | Surface Mount | |
| Pin Count | 100 | |
| Device Core | ARM Cortex M4 | |
| Data Bus Width | 32bit | |
| Program Memory Size | 1.088MB | |
| Maximum Clock Frequency | 160MHz | |
| RAM Size | 128kB | |
| Maximum Supply Voltage | 5.5V | |
| Minimum Operating Temperature | -40°C | |
| Number of Programmable I/Os | 152 | |
| Maximum Operating Temperature | 105°C | |
| Standards/Approvals | AEC-Q100, RoHS | |
| Minimum Supply Voltage | 2.7V | |
| ADCs | 12 bit | |
| Program Memory Type | FLASH | |
| Automotive Standard | AEC-Q100 | |
| Number of Timers | 79 | |
| Instruction Set Architecture | Arm Cortex | |
| Select all | ||
|---|---|---|
Brand Infineon | ||
Product Type Microcontroller | ||
Series TRAVEO™ T2G CYT2B7 Series | ||
Package Type LQFP | ||
Mount Type Surface Mount | ||
Pin Count 100 | ||
Device Core ARM Cortex M4 | ||
Data Bus Width 32bit | ||
Program Memory Size 1.088MB | ||
Maximum Clock Frequency 160MHz | ||
RAM Size 128kB | ||
Maximum Supply Voltage 5.5V | ||
Minimum Operating Temperature -40°C | ||
Number of Programmable I/Os 152 | ||
Maximum Operating Temperature 105°C | ||
Standards/Approvals AEC-Q100, RoHS | ||
Minimum Supply Voltage 2.7V | ||
ADCs 12 bit | ||
Program Memory Type FLASH | ||
Automotive Standard AEC-Q100 | ||
Number of Timers 79 | ||
Instruction Set Architecture Arm Cortex | ||
