Microchip KSZ8895RQXI, Ethernet Switch IC, 100Mbps MII, RMII, 128-Pin PQFP
- RS Stock No.:
- 236-8855
- Mfr. Part No.:
- KSZ8895RQXI
- Manufacturer:
- Microchip
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MYR43.42
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Units | Per Unit |
|---|---|
| 1 - 9 | MYR43.42 |
| 10 - 24 | MYR42.54 |
| 25 + | MYR39.53 |
*price indicative
- RS Stock No.:
- 236-8855
- Mfr. Part No.:
- KSZ8895RQXI
- Manufacturer:
- Microchip
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Network Interface | MII, RMII | |
| Data Rate | 100Mbps | |
| Package Type | PQFP | |
| Pin Count | 128 | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Network Interface MII, RMII | ||
Data Rate 100Mbps | ||
Package Type PQFP | ||
Pin Count 128 | ||
The Microchip Ethernet switch with fiber support is highly integrated, Layer 2 managed, five-port switch with numerous features is designed to reduce system cost. Designed to be used in for cost sensitive 10/100 Mbps five-port switch systems with low power requirements. Combining on-chip termination and internal LDO regulator help minimize system cost. The KSZ8895 family supports high-performance memory bandwidth and shared memory-based switch fabric with non-blocking configuration.
Static MAC table supports up to 32 entries
VLAN ID tag/untagged options, per port basis
IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port
Programmable rate limiting at the ingress and egress on a per port basis
Jitter-free per packet based rate limiting support
Broadcast storm protection with percentage control
IEEE 802.1d rapid spanning tree protocol RSTP support
Tail tag mode support at port 5 to inform the processor which ingress port receives the packet
1.4 Gbps high-performance memory bandwidth and shared memory based switch fabric with fully non-blocking configuration
VLAN ID tag/untagged options, per port basis
IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port
Programmable rate limiting at the ingress and egress on a per port basis
Jitter-free per packet based rate limiting support
Broadcast storm protection with percentage control
IEEE 802.1d rapid spanning tree protocol RSTP support
Tail tag mode support at port 5 to inform the processor which ingress port receives the packet
1.4 Gbps high-performance memory bandwidth and shared memory based switch fabric with fully non-blocking configuration