Microchip, 32bit AVR32, AT32 Microcontroller, 50MHz, 128 kB Flash, 48-Pin TQFP
- RS Stock No.:
- 127-6592
- Mfr. Part No.:
- AT32UC3L0128-AUT
- Manufacturer:
- Microchip
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 127-6592
- Mfr. Part No.:
- AT32UC3L0128-AUT
- Manufacturer:
- Microchip
Specifications
Technical data sheets
Legislation and Compliance
Product Details
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Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Family Name | AT32 | |
| Package Type | TQFP | |
| Mounting Type | Surface Mount | |
| Pin Count | 48 | |
| Device Core | AVR32 | |
| Data Bus Width | 32bit | |
| Program Memory Size | 128 kB | |
| Maximum Frequency | 50MHz | |
| RAM Size | 32 kB | |
| USB Channels | 0 | |
| Number of PWM Units | 1 x 8 bit | |
| Number of SPI Channels | 5 | |
| Number of CAN Channels | 0 | |
| Typical Operating Supply Voltage | 1.62 → 3.6 V | |
| Number of I2C Channels | 2 | |
| Number of USART Channels | 4 | |
| Program Memory Type | Flash | |
| Minimum Operating Temperature | -40 °C | |
| Number of Ethernet Channels | 0 | |
| Height | 1.05mm | |
| Width | 7mm | |
| Dimensions | 7 x 7 x 1.05mm | |
| Pulse Width Modulation | 1 (36 x 8 bit) | |
| ADCs | 8 x 12 bit | |
| Maximum Number of Ethernet Channels | 0 | |
| Instruction Set Architecture | RISC | |
| Number of ADC Units | 1 | |
| Maximum Operating Temperature | +85 °C | |
| Length | 7mm | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Family Name AT32 | ||
Package Type TQFP | ||
Mounting Type Surface Mount | ||
Pin Count 48 | ||
Device Core AVR32 | ||
Data Bus Width 32bit | ||
Program Memory Size 128 kB | ||
Maximum Frequency 50MHz | ||
RAM Size 32 kB | ||
USB Channels 0 | ||
Number of PWM Units 1 x 8 bit | ||
Number of SPI Channels 5 | ||
Number of CAN Channels 0 | ||
Typical Operating Supply Voltage 1.62 → 3.6 V | ||
Number of I2C Channels 2 | ||
Number of USART Channels 4 | ||
Program Memory Type Flash | ||
Minimum Operating Temperature -40 °C | ||
Number of Ethernet Channels 0 | ||
Height 1.05mm | ||
Width 7mm | ||
Dimensions 7 x 7 x 1.05mm | ||
Pulse Width Modulation 1 (36 x 8 bit) | ||
ADCs 8 x 12 bit | ||
Maximum Number of Ethernet Channels 0 | ||
Instruction Set Architecture RISC | ||
Number of ADC Units 1 | ||
Maximum Operating Temperature +85 °C | ||
Length 7mm | ||
32-Bit AVR UC3 Microcontrollers
AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions.
To fully exploit the power of a 32-bit architecture, the AVR32 is not binary compatible with earlier AVR architectures. In order to achieve high code density, the instruction format is flexible providing both compact 16-bit and extended 32-bit instructions. While most instructions are 16-bit, powerful 32-bit instructions are implemented to further increase performance. Compact and extended instructions can be freely mixed in the instruction stream.
To fully exploit the power of a 32-bit architecture, the AVR32 is not binary compatible with earlier AVR architectures. In order to achieve high code density, the instruction format is flexible providing both compact 16-bit and extended 32-bit instructions. While most instructions are 16-bit, powerful 32-bit instructions are implemented to further increase performance. Compact and extended instructions can be freely mixed in the instruction stream.
The Microchip AT32UC3L 32-bit system-on-chip microcontroller is based on the AVR32 UC RISC processor running at frequencies up to 50MHz. It operates on single 1.62V to 3.6V power supply. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern and real-time operating systems. The Secure Access Unit (SAU) is used together with the MPU to provide the required security and integrity. The Peripheral Direct Memory Access (DMA) controller enables data transfers between peripherals and memories without processor involvement, also drastically reduces processing overhead when transferring continuous and large data streams. The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. The Peripheral Event System allows peripherals to receive, react to, and send peripheral events without CPU intervention. The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software.
Secure Access Unit (SAU) providing User-defined Peripheral Protection
High-performance Data Transfers on Separate Buses for Increased Performance
Internal High-speed Flash of 128 Kbytes
Internal High-speed SRAM of 32 Kbytes
Flash Security Locks and User-defined Configuration Area
Auto vectored Low-latency Interrupt Service with Programmable Priority
Peripheral Event System for Direct Peripheral to Peripheral Communication
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Six 16-bit Timer/Counter (TC) Channels
PWM Channels on All I/O Pins (PWMA)
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
Integrated Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace
Package type of 48-pin TQFP/QFN/TLLGA (36 GPIO Pins)
High-performance Data Transfers on Separate Buses for Increased Performance
Internal High-speed Flash of 128 Kbytes
Internal High-speed SRAM of 32 Kbytes
Flash Security Locks and User-defined Configuration Area
Auto vectored Low-latency Interrupt Service with Programmable Priority
Peripheral Event System for Direct Peripheral to Peripheral Communication
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Six 16-bit Timer/Counter (TC) Channels
PWM Channels on All I/O Pins (PWMA)
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
Integrated Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace
Package type of 48-pin TQFP/QFN/TLLGA (36 GPIO Pins)