Infineon NOR 128Mbit CFI, SPI Flash Memory 8-Pin WSON, S25FL128SAGNFV000
- RS Stock No.:
- 181-8392P
- Mfr. Part No.:
- S25FL128SAGNFV000
- Manufacturer:
- Infineon
Bulk discount available
Subtotal 84 units (supplied in a tray)*
MYR1,518.468
FREE delivery for orders over RM 500.00
In Stock
- 285 unit(s) ready to ship from another location
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per Unit |
|---|---|
| 84 - 165 | MYR18.077 |
| 168 + | MYR17.257 |
*price indicative
- RS Stock No.:
- 181-8392P
- Mfr. Part No.:
- S25FL128SAGNFV000
- Manufacturer:
- Infineon
Technical data sheets
Legislation and Compliance
Product Details
This family of devices connect to a host system via a SPI. Traditional SPI single bit serial input and output (Single I/O or SIO) is
supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface
is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer
address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be
programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,
asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast performance required by a variety
of embedded applications. They are ideal for code shadowing, XIP, and data storage.
supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface
is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer
address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be
programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,
asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast performance required by a variety
of embedded applications. They are ideal for code shadowing, XIP, and data storage.