Nexperia 74AUP1G07GW,125 Open Drain Buffer, 5-Pin TSSOP

  • RS Stock No. 165-9929
  • Mfr. Part No. 74AUP1G07GW,125
  • Manufacturer Nexperia
Technical data sheets
Legislation and Compliance
RoHS Certificate of Compliance
COO (Country of Origin): MY
Product Details

74AUP1G/74AUP2G/74AUP1T Family, Nexperia

74AUP Family

Industry-standard Advanced Ultra-low Power (AUP) logic family products for ultra-low power consumption, small footprint logic solutions for use in 1.8 V and mixed 1.8 V / 3.3 V circuit applications. The AUP logic family offers the following features:

Wide supply voltage range: 0.8 to 3.6V
Schmitt-trigger inputs for high noise immunity
Very low dynamic power dissipation
Enhanced ESD protection
Speed/power optimization

Specifications
Attribute Value
Logic Family AUP
Schmitt Trigger Input No
Input Type Single Ended
Output Type Open Drain
Mounting Type Surface Mount
Package Type TSSOP
Pin Count 5
Maximum Low Level Output Current 4mA
Maximum Propagation Delay Time @ Maximum CL 20.7 ns @ 30 pF
Dimensions 2.25 x 1.35 x 1mm
Minimum Operating Temperature -40 °C
Height 1mm
Minimum Operating Supply Voltage 0.8 V
Maximum Operating Temperature +125 °C
Maximum Operating Supply Voltage 3.6 V
Length 2.25mm
Propagation Delay Test Condition 30pF
Width 1.35mm
3000 In Global stock for delivery within 4 - 6 working days
Price Each (On a Reel of 3000)
MYR 0.348
units
Per unit
Per Reel*
3000 +
MYR0.348
MYR1,044.00
*price indicative
Related Products
The 74VHC595FT is an advanced high speed 8-BIT ...
Description:
The 74VHC595FT is an advanced high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The 74VHC595FT contains an 8-bit ...
Dual 4-channel analog multiplexer/demultiplexer, The 74HC4052-Q100, 74HCT4052-Q100 is ...
Description:
Dual 4-channel analog multiplexer/demultiplexer, The 74HC4052-Q100, 74HCT4052-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard no. 7A. The 74HC4052-Q100, 74HCT4052-Q100 is a dual 4-channel ...
The 74HC4051-Q100, 74HCT4051-Q100 is a high-speed Si-gate CMOS ...
Description:
The 74HC4051-Q100, 74HCT4051-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The 74HC4051-Q100, 74HCT4051-Q100 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight ...
The 74HC574: 74HCT574 is an 8-bit positive-edge triggered ...
Description:
The 74HC574: 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold ...